Technical Summary for Patent No US 7,327,803 B2
Patent Title: Systems and Methods for Vector Power Amplification
Inventors: David F. Sorrells, Gregory S. Rawlins, and Michael W. Rawlins
Patent No.: US 7,327,803 B2
Date of Patent: Feb. 5, 2008
Comments: Deuk Heo (Deukhyoun Heo or D. Heo), 4/30/08
Introduction
The insatiable demand for a high data rate in wireless communications has led to the
development of efficient modulation methods and linear communication system architectures.
Efficiency and linearity of power amplifiers are two important parameters that need to be
focused on improving the performance of communication systems. Technical solutions for
these issues can be classified as efficiency enhancement and linearization techniques. Some
of these solutions are Cartesian feedback [1], digital pre-distortion [2], feed-forward
linearization [3], polar transmitter [4] and out-phasing amplifier techniques [5-8].
The out-phasing concept was presented in the 1930s as an approach to high-efficiency
and high-linearity power amplifier development [5]. Out-phasing has been implemented for
wireless communication applications under LINC (linear amplification with nonlinear
components) [9]. The out-phasing amplifier takes an envelope modulated signal and
decomposes the signal into out-phased constant envelope signals, which are amplified by
highly efficient power amplifiers. Then, the output power of each branch is combined to
produce an amplified envelope modulated signal.
The separation of envelope modulated signals into out-phased constant envelope signals
is accomplished by SCS (signal component separator). This approach takes advantage of the
constant envelope feature of the two out-phased signal components. The out-phasing system
is insensible to the nonlinear characteristic of the two individual power amplifiers. Even
though the power amplifiers are nonlinear, the final output signal can be highly linear. In
addition, each amplifier can be operated in a power efficient mode, and the overall power
efficiency of the system could be greatly improved. Therefore, the out-phasing power
amplifier is a promising approach that offers high linearity and high efficiency power
amplifiers for communication systems.
In the out-phasing (LINC) technique, overall power efficiency is dependent on two main
components. While the power amplifier consists of two signal paths having a high-efficiency
amplifier with a power combiner at the output, the efficiency of the LINC power amplifier is
affected not only by the amplifiers, but also by the combiner. As the individual amplifier
efficiency can be maximized for a constant envelope signal by operating it in a high
efficiency amplifier (non-linear amplifier), the overall efficiency of the LINC amplifier
remains dependent on the power combiner. The overall power efficiency is obtained from the
product of power amplifier efficiency and combiner efficiency.
There are two kinds of combiners at the output stage. The hybrid combiner is a lossy
combiner with high isolation between two signal paths. General structures of this type include
the hybrid coupler and the Wilkinson combiner. Due to the isolation between the two signal
paths, these types of combiners provide good linearity. However, the efficiency of these
structures degrades rapidly at the increased crest factor of the signal. The other type of output
stage combiner is the lossless out-phasing combiner. This type of combiner includes the
lossless Wilkinson-type combiner without the isolation resistor, and a combiner that includes
two quarter-wavelength transmission lines and shunt reactance at the input of each
transmission line. This is referred to as a Chireix out-phasing combiner.
Patent Analysis
Overall Assessment
This patent presents three types of out-phasing power amplifiers based on vector power
amplification (VPA) and includes mathematical analysis to prove the concepts presented. The
Cartesian 4 branch VPA has some potential advantages compared to the 2 branch amplifier in
MMIC (monolithic microwave integrated circuit) implementation using low breakdown
voltage devices such as scaled CMOS devices. However, this structure has more amplitude
and phase imbalance issues between 4 branches, and total power efficiency issues due to its
two-step power combining scheme. In addition, there is a critical flaw in the claimed power
combining technique, which is the wiring of the outputs of each power amplifier in the
different branches. This flaw is found in all of the claimed vector power amplifiers
throughout the patent.
The Cartesian-polar 2 branch VPA architecture and direct Cartesian 2 branch vector
power amplifiers represent a type of general out-phasing amplifier [6-8] with their claimed
power combining technique based on wiring method. Therefore, the same problems of the
out-phasing amplifiers are included in these architectures except the power combining issue
in the claimed wiring methodology.
In the out-phasing amplifier, there are several technical limitations:
1. Bandwidth issue: A phase modulated signal has more than 10 times wider bandwidth than
the original signal [10-11].
2. Output stage power combining issue: The power combining of different signals is quite a
tricky problem in this kind of amplifier architecture, including power combining efficiency,
load variation, bandwidth, and monolithic integration issues.
3. Phase and delay imbalances: Two different signal branches should be ensured to achieve
the same delay and phase. To achieve this balance, complicated imbalance calibration
techniques should be presented according to the data rate of the communication.
Unfortunately, this patent does not suggest how to solve the aforementioned technical
issues in the proposed out-phasing amplifiers. The claimed patent explains the idea of the
theoretical operation of three different vector power amplifier architectures, rather than
technical solutions of each implementation.
Three Claimed Vector Power Amplifiers
A. Cartesian 4 branch Vector Power Amplifier
In Figure 5, Cartesian 4 branch VPA is explained. I-Q modulation method is based on
two different output phasing amplifiers. I and Q signals are built up using two different outphasing
amplifiers. The phase modulators 520 and 530 provide two constant envelope signals
of IU(t) and IL(t), and two constant envelope signals are amplified separately by the
saturation amplifiers of 562 and 564, respectively. The amplified signals are combined with a
572 power combiner to generate a complex envelope I-component signal of i(t). Similarly,
q(t) is generated through a 574 combiner. Finally, two non-constant envelope signals of i(t)
and q(t) are combined by a 576 power combiner. In this architecture, the high efficient power
combiners should be available, and the four different paths should be balanced. However, the
patent did not provide detailed instructions for implementation of this architecture. In Figure
7 and Figure 8, the output power cannot be shorted without the power combiner. For example,
770, and 772, 774, and 776 are shorted. Then, the load impedance of each power amplifier
will be varied, according to the other power amplifier output conditions.
There are some potential advantages in this 4 branch VPA to implementing an outphasing
amplifier. To implement an on-chip power amplifier using low breakdown devices
such as scaled CMOS, it would be beneficial to have 4 branches, because the power
requirement of the power amplifier in each branch would be reduced, which is appropriate for
scaled CMOS devices with low breakdown voltages (limited power handling capability).
However, in that case, there will be two important hurdles to overcome. One hurdle is the
power efficiency of two-step power combining and phase and delay imbalance of each power
amplifier branch.
In the presence of path imbalance, the output is the vector sum of the expected signal and
a distorted signal, due to imperfect cancellation of quadrature signal. In addition, the
spectrum of phase modulated quadrature signal extends far into adjacent frequency channel
[12]. As a result, the incomplete cancellation of wideband components leaves a residue of
signals in adjacent channels and alternate channel interference. Therefore, a calibration
circuit should be implemented to compensate for these error effects in real time. In this 4
branch VPA, there will be more possibility of imbalances in each power amplifier branch,
and the calibration load of the feed back circuit will increase as the data rate increases with
wider bandwidth requirements. Other than this imbalance issue, frequency modulation is
involved in order to upconvert the phase modulated baseband signal to the carrier frequency.
Quadrature error also results in similar effects on the output spectrum. Due to its random
behavior, it is not easy to compensate for quadrature error. Nowadays, the evolution of DSP
(digital signal processing) technique has made it possible to implement SCS in software.
The main flaw of the claimed VPA is the power combining method. The idea for this
combining technique is explained in Figure 29, but the near zero-impedance current
combining method does not work for combining different powers in different branches. To
combine power output, we need to use a high efficient power combiner with good isolation
between branches, impedance match and wide bandwidth. In the suggested combiner in the
patent, the output of one power amplifier will affect the load impedance of the other power
amplifiers, so the output power levels will be changed. Also, for the near zero current
combiner in a higher frequency region, it is not easy to design the required matching network
with a low loss and wide bandwidth. Furthermore, it is not possible to combine different
powers using this method. While this is a possible method for signal combining, power
combining is different. Signal combining is much simpler than power combining. The
claimed wiring method will not function for power combining, which is main flaw in all three
claimed VPA architectures.
B. Cartesian-polar 2 Branch Vector Power Amplifier
Figure 10 shows Cartesian-polar 2 branch VPA architecture. In a conventional polar
transmitter [4], the phase and amplitude information have different parallel paths. Therefore,
the accurate timing between amplitude and phase path is the key technical issue to implement
polar transmitters. However, in the suggested out-phasing architecture, the phase modulated
signals are generated by 1016 by combining I-phase 1012 and Q-phase 1014, and the
amplitude modulation is implemented using an out-phasing amplifier. In Figures 9A and 9B,
two different phase control blocks are explained; the first controls the phase information, and
the second controls the amplitude information by changing the phase. In this architecture, the
phase modulated signals should have a much larger bandwidth than the original signal, as
mentioned for the bandwidth issues. The 1060 and 1062 phase modulators should be faster
than the conventional out-phasing amplifier; also, it is more difficult to balance between two
out-phasing signal paths. In my opinion, this architecture is more difficult than a conventional
out-phasing amplifier, and there are no major benefits.
C. Direct Cartesian 2 Branch Vector Power Amplifier
In Figures 14 and 15, the direct Cartesian 2 branch vector power amplifier is explained.
This architecture is the same as that of the conventional out-phasing amplifier. Two constant
envelope signals with different phases are combined at the output stage. The common phase
in Figure 14 provides the phase information, and the difference phase generates the envelope
information. In Figure 15, two phase modulators of 1520 and 1530 control the phase
information of each branch. Ux 1528 and Uy 1526 are applied to 1250 to control the phase of
the upper branch, and Lx 1536 and Ly 1538 are applied to 1530 to control the phase of the
lower one. The average of the upper and lower branches becomes the common phase to give
phase modulation information, and the difference of the upper and lower branches is the
difference of the phase to modulate the envelope information.
Conclusion
The technical merits and issues of three vector power amplifiers are explained. Basically,
the claimed vector power amplifier concept comes from the out-phasing amplifier, so these
architectures have the same technical concerns as the out-phasing amplifiers. The key
problem is that the patent didn’t suggest any idea about how to solve the issues in the
implementation of the out-phasing amplifier.
In section 3.5, the near zero impedance power combining method has been suggested, but
the proposed method is not expected to work because of the impedance change from such
low impedance to the required system impedance. In addition, the power combiner should not
change the output load impedances of the other amplifiers, or should be controllable to
provide enough output power. This combining technique in the patent is not viable for
providing enough bandwidth and efficiency, and this is not a power combining technique
with good isolation between power amplifier branches.
The suggested combining methods are only valid for the current signal combining
architecture. Furthermore, using the impedance matching network to convert the near zero
impedance combiner to the desired system impedance will be difficult. In such a large
impedance changing network, a very high Q circuit is required. However, a high Q matching
network creates a bandwidth issue.
Therefore, the claimed VPAs will not be feasible to implement without incorporating
high efficiency power combining technique and good calibration technique for signal
imbalance in high data rate operation mode.
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